Overlay is a yield delimiter in current technologies, especially for contacts/vias covering metal. That is, overlay errors are a known source of yield loss in semiconductor manufacturing. Overlay can be as much as 25% of the minimum wire width in 22 nm technologies. As an example, overlay error between contact and metal can lead to poor contact between metal and via which degrades contact resistance and increases risk of electromigration. For this and many other reasons, overlay accuracy between two patterns, e.g., metal layer and contact or via is generally considered a big challenge for increasing yield.
Current methods of finding structures at risk due to overlay simply consider coverage area between layers, but this is an inaccurate measure since the same coverage areas could still mean different risk in presence of overlay. For example, Optical Rule Checking (ORC) predicts failure of wafer shapes due to process proximity effects. However, using ORC is a very complicated process, especially when being performed on mask shapes. Also, ORC does not provide an accurate method for detecting structures at risk due to overlay.